Mixed-base notation for computing machines



Feb. 6, 1962 Filed July 12, 1957 v R. E. WILLIAMS MIXED-BASE NOTATIONFOR COMPUTING MACHINES 15 Sheets-Sheet 1 3 F /P o l I w w w w 0 L FIG.I

/ COUNTING PULSES IN 2 I RESET 6 u l0 CARRY PULSE ouT 1' PERMUTE 8 T0zERo 0 RESET FIG.2

' READ IN UNITS THOUSANDS TENS HUNDREDS 4o CARRY 44 CARRY 43 CARRY 42 38l RINGOF3 4 3 4: 3 4; 3 4

M a DECADE MB DECADE MB DECADE MB DECADE COUNTER COUNTER COUNTER COUNTERl 1 3s 35 34 33 Richard E.Williams 3 INVEN'IOR BY 41/, MM ME ATTORNEYSFeb. 6, 1962 R. E. WILLIAMS Filed July 12. 1957 13 Sheets-Sheet 2 READIN SUBTRAHEND START 'v CLOCK PULSE o O v l GATE GENERATOR OPENED BYCLOSURE 52 I STOP OF SWITCH l6 I ovci READ 65 5 READ IN MINUEND NEGATIVEFIG. 4 NUMBER,ALARM' RECOMPLEMENT POLARITY 72 INVERTER SUBTRACT INPUT 074 ADD OVERFLOW STOP OR NEGATIVE 77 NUMBER ALARM FIG. 5

Richard E. Williams INVENTOR ATTORNEY/S Feb. 6, 1962 Filed July 12, 1957R E. WILLIAMS MIXED-BASE NOTATION FOR COMPUTING MACHINES 13 Sheets-Sheet3 MULTIPLIER READ m 7 MIXED BASE opsrop PULSEM PRIMARY 9| a0 MULTIPLIERCLOCKPULSE 82 REGISTER GENERATOR 93 84 9O STEP DOWN INVERTER a9 88 8|GATE MULTIPLICAND L READ IN 83 87 92 :T I l QQ STEP MIXED BASE READPULSE NoN-DEsTRucTIv OUT CLEAR MULTIPLICAND I CIRCU'T REGIsTER 9s REsETREADOUT 93 MIXED BASE MIXED BASE 86 OVERFLOW PRODUCT F166 ACCUMULATORCARRY ACCUMULATOR REGISTER REG|5TER HUNDREDS TENs UNITS Ice FM TIE FmI04 AULILFL DOUBLE fmp PULSE PULSE GENERATOR GENERATOR (x2) (x3) "JULJLI'LFUUU1 E RING OF I sEvEN I05 Ioo FIG. 7

Richard E.Willioms INVENTOR 7/ BY W W ATTORNEYS Feb. 6, 1962 R. E.WILLIAMS 3,019,975

MIXED-BASE NOTATION FOR COMPUTING MACHINES Filed July 12. 1957 15Sheets-Sheet 4 HUNDREDS TENS UNITS FIG 8 11 M2 mm H: mm ..o

7 RING OF OUTPUT DIRECT COUNT EVEN n4 REVERSE INVERTU COUNT IOO'S f IO'SUNITS FIG.9 w n1 INVERTER-H 9 RING RING RING OF OF OF v NINE TEN ELEVENMULTIPLIER CLOCK PULSE /|25 STEP DOWN GENERATOR I33 GATE I26 2 READ READ29 OUT OUT I 4 .MULTIPLICAND Richard E.Wil|iams I36 ACCUMULATORS NINVENTOR FIG. l0

WWW BY W W ATTORNEYS 1962 R. E. WILLIAMS 3,019,975

MIXEDBASE NOTATION FOR COMPUTING MACHINES Filed July 12, 1957 13Sheets-Sheet 5 I49 I58 150 0 V N 'k/ l5! 0 AND V H r AN F Q 2 FIG. llRichard E. Williams INVENTOR WWI/W BY 4 M KW ATTORNEYS Feb. 6, 1962 R.E. WILLIAMS MIXEDBASE NOTATION FOR COMPUTING MACHINES Filed July 12.1957 15 Sheets-Sheet 6 R 5 m .mN E w E1 0 r a h 0 l 2 M B C M m 7 w 6. RO I O M M 4 4 w... 0 2 m 9 2 F 6\m.... m N 7 N N 2 Aw 7 M A A m A 4 4 4M l 4 I ATTQRNEYS Feb. 6, 1962 E. WILLIAMS Filed July 12. 1957 13Sheets-Sheet 7 206 START 208 GATE 210 209 22o DIVIDE CLOCK i 20 STOP BYTEN PULSE 5E START F INVERTER GENERATOR 207 GATE 1 TsToP 2oo l 2o| 0FIG. 15 2l5 203 r 2|7 I 2l7 PREsET PRESET uWlDTHGATYIG WIDTH (4T) GATE(9T) sTART TENs 2 5 NTE 2 ZERO PERMUTE MULTIPLIER RING 9 I ISI 65PRODUCT OR RING I62 0 AN MULTIPLCAND RING 2 I64 |e5 AN Richard E.Williams ATTORNEYS Feb. 6, 1962 R, E. WILLIAMS 3,019,975

MIXED-BASE NOTATION FOR COMPUTING MACHINES Filed July 12. 1957 13Sheets-Sheet 8 0 ND 0 l I72 I AND I 2 I73 2 EK- 2 0 I74 DINN- FIG. l4

Richard E. wllllums INVENTOR ATTORNEYS Feb. 6, 1962 Filed July 12. 1957R E. WILLIAMS MIXED-BASE NOTATION FOR COMPUTING MACHINES 13 Sheets-Sheet9 ,253 r252 (2m ,250 BLANKING DELAY DIVIDE BY CLOCK CIRCUIT CIRCUIT EGHTPULSE INVERTER GENERATOR E SEIQUENCING 6:51 s 265 t 2 CLOSE SEQU- zsgENCING GATES 275 277 START START i265; $267 $261 $269 $279 I 27,4 FWGFWG FWG FWG FWG FWG FWG FWG FWG IT 2T 6T IT 7T 5T IT 2T OT SUBTRACT 210N FIG.|6

Richard E. Williams INVENTOR BY 4/, W M

ATTORNEYS Feb. 6, 1962 E. WILLIAMS 3,019,975

MIXED-BASE NOTATION FOR COMPUTING MACHINES Filed July 12. 1957 13Sheets-Sheet 1O DIVIDE BY CLOCK 7 2g??? DELAY SEVEN 4* PULSE INVERTERGENERATOR c 320 sTART T GATE TSTOP L w GATE S Op 353- I J, I 332/ '*1 IFWG FWG FWG 3T 6T ET 351 CARRY CARRY 3|? TENS UNITS HUNDRED DECADEDECADE COUNTER UNT COUNTE 3T3 3L5 3:4

SUBTRACT 210 FIG. I?

Richard E. Williams INVENTOR ATTORNEYS Feb. 6, 1962 R. E. WILLIAMS3,019,975

MIXED-BASE NOTATION FOR COMPUTING MACHINES Filed July 12, 1957 13Sheets-Sheet 11 551 sso ,400

CLOCK BLANK'NG DELAY PULSE GENERATOR 555 START GATE GATE FIG. 22

CARRY am I t 572- 1 FF F F FF FF, FF FF FF FF FF 25s 12a 64 32 l6 s 4 21 i i 573 /570 OVERFLOW DET. ADD 302 I 57' (MOD 210) 574 i %L j 5,6,75,6,7 MIXED BASE MIXED BASE 0o 0 o 000 000 III m 136 lol 36 I0! I OOI|2o OOI IH o|o I 010 043 0| on 154 I00 I26 aoo 042 no an no 025 RichardE.Wil|ioms FIG. l8 FIG. [9 INVENTOR ATTORNEYS Feb. 6, 1962 R. E.WILLIAMS 3,019,975

MIXED-BASE NOTATION FOR COMPUTING MACHINES Filed July 12. 1957 13Sheets-Sheet l2 DIVIDE BY CLOCK TEN PULSE INVERTER GENERATOR 4|| START4OI 4o5 400 A02 /403 404% STOP EARLY STOP EARLY EARLY GATE GATE GATE 417I ,4Io 42I 425 29 I LATE START LATE A sTART LATE sTART 425 40 GATE 40GATE GATE 420 STOP AND 437 450 III N PBG ST A 430 UNITS 44' 46' DECADE\TQ' I PBG 5T couNTER AN 0R 43I 454 E A OOI PBG 9T 455 g H 432 45s 0 0'0p 81' TENS m DECADE 45| 433 4 P86 7T COUNTER 0 457 E 434 PBG 3T E EO 462O 435 OR PEG 2T HUNDREDS 453 COUNTER 463 458 459 7 Richard E. WilliamsINVENTOR FIG. 20

BY MM ATTORNEYS E. WILLIAMS MIXED-BASE NOTATION FOR COMPUTING MACHINESFiled July 12. 1957 13 Sheets-Sheet 13 DIVIDE BY 4o CLOCK 4OQ SEVENPULSE INVERTER GENERATOR STARTc 4o2 L407 ,403 osh & ,404 STOP LATE EARLY2 2 LATE EARLY STOP LATE EARLY STOP GATE GATE GATE GATE 1 GATE GATE 1sTART sTART 426 UNITS TENS HUNDREDS DECADE DECADE COUNTER /429 AN ORRING 50o FIG.2|

INVENTOR ATTORNEYS United States Patent Filed July 12, 1957, Ser. No.671,662 31 Claims. (Cl. 235-155) The present invention relates generallyto digital com-' puters employing congruence algebra as a basis for itsalgorithms, and more particularly to digital computers employing mixedbase notation, or digital words consisting of residue systems or seriesof digits rooted, respectively, in diiferent bases or moduli.

Briefly describing the present invention, I define a mixed base digitalword as a series of digits rooted each in a different base, asdistinguished from the conventional digital word wherein all the digitsare rooted in the same base system. It may be shown, if the roots ormoduli of the system are relatively prime, that a sequence of digitalwords may be generated which contains no ambiguitiesover a range ofwords equal to the product of the moduli. These words are generated bysimultaneously. adding units to each order or line of the word, withoutcarry,

which leads to techniques for rapid processing in the.

imal system, and combination of these such as the binary decimal system,are typical of common base systems, i.e., systems wherein each digit ofa word employs the same base or modulus.

The generalized formula for typical common base numbers is t N E A M Thedigit A of index K is multiplied by the common base or modulus raised tothe power of the index, and the word is a sum of digits. For example,the word 863 =[8 .10 ]+[6 l0]+[3 10]. We may depart from systemsemploying a common root, Without departing from the summationconvention. Such systems in fact employ mixed bases, but any number isrepresented by the sum of its digits, each digit being expressed to adifferent base, but the different bases are weighted, therefore carry orborrow v operations are required in arithmetical operations. I

In accordance with one aspect of the present invention mixed basenotation is employed, but there is no columnar weighting, i.e., eachcolumn has the same weight,

and addition of the number unity to a word, in the latter notation, isaccomplished by adding unity to each line or position of the word. i g

-It can be shown that addition of unity to each of a series of digitsrooted in moduli which are relatively prime in pairs yields a series ofnon-redundant digital words, over a range of values equal to the productof the moduli. A simple illustration of such a system might employ themoduli 3 and 4, which are relatively prime. In such case 12:3 X4 numbersmay dundance, asfollows. 4

be expressed without re pline.

v moduli m m ice 2 SCHEDULE A Mixed Base Notation Decimal NotationModulo Modulo 3 4 The general principles of congruence algebra have beenunderstood for a long time, the great mathematician Gauss being thepredominating originator of'the disci-,

Reference is made palticularly to The Elements of the Theory ofAlgebraic Numbers, by Reid, 1910,

published by Edwards Brothers, Inc, for a complete exposition; a briefrsurn of the algebra, and of some of the permitted algorithms beingherein provided.

CONGRUENCE ALGEBRA We can express the fact aEb mod m by writing ab=km ora=b+km, where k is an integer, but the notation aEb mod m, which is dueto the mathematician Gauss, has the great advantage of placing inevidence the analogy between congruences and equations, and it is. foundthat most of the transformations and algorithms to which equations aresubject are also applicable to congruences.

We have, as a direct consequence of the definition of congruences, thatif azb rnod m and bzc mod m that azc mod m.

Addition, subtraction, multiplication by an integer and multiplicationof congruences are all possible in the. theory of congruences. Forexample, if a ab mod m and a zb mod m, then a ia zb ib mod m. If

azb mod m, andc is any. numbenthen ac=bc mod m; if 1 5171 mod m and a zbmod m, then a a zb b mod m.

While addition, subtraction and multiplication present nodifliculties,-and proceed in accordance with the above formulae, theproblem of division is not so simple. For

example 8214 modulo 6, but 4 7 modulo 6, i.e., the. two sides of thecongruence cannot be divided by 2 in.

In fact, it is found that division of the I the case given. two sides ofa congruence by a common factor is permissible only if the modulus isprime to the division factor. If it is not so prime then not only mustthe two sides of the congruence be divided but the modulus itself mustbe'divided by the division factor.

A last result of great value may be expressed as follows:' If a iscongruent to b with respect to each of the l, where l is the leastcommon multiple of m m relative to each other, in which case 1 is theproduct of the moduli. For the purpose of'providing simple ex U amplesof the above theorems, reference is made to the hereinabove providedSchedule A. The schedule'shows" Patented Feb. 6, 1962 m,,, then a iscongruent to b modulo 1 This is especially important where the moduliare prime the numbers from to 11 in the decimal system of notation,there being accordingly 12 decimal numbers. The corresponding numbers ina mixed base system modulo 3 by 4 are also illustrated. The first columnis modulo 3 and the second column modulo 4. It is then apparent from theschedule that each decimal number corresponds with a different mixedbase number. It may be observed from the table that addition of unity tothe decimal column is accompanied by an addition of unity to each of themixed base columns and this is true regardless of the modulo employed.It may also be observed that addition of any two mixed base numbersprovides a third mixed base number which is equivalent in the decimalsystem to the sum of the original two numbers taken in the decimalsystem. It may also be observed that any mixed base number may bemultiplied in respect to both its columns by a decimal digit, and thatthe result in the mixed base notation is equivalent to a multiplicationof a decimal number by the corresponding multiplier. For example, if wemultiply 2X3 in the decimal system, we arrive at the product 6. If wemultiply 2-2 in the mixed base system by 0-3, column for column, wearrive at the answer 06 which is 0-2 modulo 3 and 4, since 050 mod 3 andsince 652 mod 4. 0-2 equals 6 in decimal notation.

It may further be observed that two mixed base numbers may bemultiplied, giving a resultant mixed base number equal to the product ofthe corresponding decimal numbers. For example, we may multiply 2 3 inthe decimal notation, by multiplying 22 03 in the mixed base notation.This gives a product 0-6, 050 mod 3, and 652 mod 4, so that again wearrive at a product 0-2 in the mixed base notation, which is equivalentto 6 in the decimal notation.

Certain other elementary facts may be deduced by inspection of theschedule. For example, advance of one of the columns withoutcorresponding advance of the other column corresponds to an addition ofk times the modulus of the other column, where k is an integer. Forexample, the decimal number 4 is 1-0 in 3 X4 mixed base notation.Addition of 1 to the first column of the mixed base number provides anew mixed base number 2-0 which is equivalent to 8 and corresponds with4 plus 4.

Many mathematical operations are readily possible in the mixed basenotation which are difficult in other notations, and these will becomeevident as the description proceeds.

Examination of Schedule A reveals that a mechanical or electrical analogof the left-hand column in mixed base notation, can readily be createdby utilizing a ring counter of three states, and the right-hand columnthrough use of a ring counter having four states. The cyclic patterns ofthe digits within each column are automatically yielded by the rings intheir progressive stepping actions, provided both rings are stepped foreach addition of unity.

A somewhat more elaborate mixed-base gamut using four relatively primemoduli may involve the moduli 5, 7, 8, and 9. Resolution in this case isequal to one part in 2520= 7 8 9. The same columnar cyclic ring countprocess observed in Schedule A (modulo 3 and 4) applies in thequadmodulo case except that in the example shown rings having 5, 7, 8,and 9 states, respectively, are required. Additional relatively primemoduli can be added to the quad-modulo system to yield considerableincreases in gamut capacity. A column of modulo 11 can, for example, beadded to yield a 27,720 word capacity; and a further addition of a ringof 13 will yield a capacity of 260,360 words. It is thus seen that themixedbase notation can conveniently be used to yield great 4Arithmetz'cal functioning Perhaps the greatest single asset of themixed-base notation lies in its ability to perform the simplerarithmetical functions such as addition, subtraction, andmultiplication, by economical implementation. The economy ofimplementation results primarily from the elimination of digital carryrequirements. Addition of mixed base digits thus consists of merelystepping columnar rings in completely independent fashion by steps equalto the mixed-base digits to be added. The total time required for anaddition of two numbers thus is never longer than the time required tostep the largest modulo-minus-one present.

Mixed-base subtraction can take the usual form of compleinentaryaddition. The complement of a word in mixed-base notation is yielded bysubtracting each digit of the Word from its respective modulus. Thissimplified subtraction process may in some cases yield a complementarydifference which requires special detection in a mixed-base system. Inmost cases if the complementary number. is an interim step in thecomputing process, the number will yield no eventual ambiguity, providedthat the final result falls in the gamut of true numbers.

In the process of multiplication, once again, the operation is entirelycolumnar in nature and no carry is required. A typical multiplicationoperation can be performed through successive additions, and the maximumnumber of steps required will never exceed the highest modulo-minus-onesquared, in accordance with one procedure, or the highestmodulo-minus-one in another. Like the other simple arithmeticalprocesses, multiplication is rapidly yielded when mixed-base notation isutilized.

The usual problems of overflow will be observed in a computing machineutilizing mixed-base notation. It is important to note, however, that anumber expressed in overflow form will be modulo the machine capacity.Normal operations can thus proceed provided the proper multiple of themachine capacity is added to the result at readout. The customary shifttechnique of accommodating overflow is someimes diflicult to implementin the mixed-base system, as columnar shift requires modular conversion.It is considered generally advisable to use mixed-base notation in thoseapplications where overflow conditions can be reliably predicted inadvance and accommodated by suitable subtraction or addition processes.Certain subsidiary devices, such as weighted mixed-base conversiondevices, can yield the necessary information; but machine speed islowered, and complexity added. In general, it will prove more economicalto add another modular ring to multiply the capacity of a machine, whereadditional capacity is required.

Decimal to mixed-base conversion and vice versa In order to convert anydecimal number to its mixedbase equivalent, it is merely necessary todivide the decimal number successively by the various moduli of themixed-base system and express the mixed-base number as the remaindersper modulus. For example, the decimal number 1,000 can be expressed inthe 5, 7, 8, 9 mixedbase system as follows:

a=remainder =0 b =remainder Q c=remainder -10 d=remainder The mixed-baseword is thus 0601.

In order to convert a mixed-base word to its decimal equivalent a moreinvolved process is required. Typical steps are as follows for aquadmodulo system, the extension being straight-forward for othermodular groups.

(1) Find the decimal equivalents for the words in mixed-base notation1000, 0100, 0010, and 0001. The first word is known to be anexactmultiple of the moduli m m and m since the remainders in each case are0. It is then merely necessary to discover such a multiple which will inaddition yield a remainder of one when divided by the first modulo, mThe existence of such a multiple is assured by the relatively primechoice of mod uli. In the 5, 7, 8, 9, scheme chosen, for example, thelowest common multiple used for-the first digit, a, is found to be2,016. (7, 8, and 9 are factors oft20l6, and 2016 divided by 5 leaves aremainder of one.) By a similar process the multiples for the remainingdigits are found to be 1800, 945, and 280 respectively.

(2) Each expressed digit of the mixed-base Word to be evaluated ismultiplied by its associated multiple and the entire results summed.

(3) The sum is divided by the productof the moduli to yield a remainderwhich expresses the decimal equivalent.

For example, to find the decimal equivalent of the mixed-base number3678 in the 5, 7, 8, 9 mixed-base scheme, it is merely necessary to findthe remainder of 20l6a+l800b+945c+280d upon division by 2520.Substituting three for a, six for b, etc., and dividing as indicated, itis found that a remainder of 503, the decimal equivalent, results. T

It is, accordingly, a primary object of the present invention to providea system for digital computation, which employs mixed-base numbers, andprinciples of congruence algebra in'its implementation.

It is afurther object of the present invention to provide a system foradding two mixed-base words, and for sub tracting two mixed base words.

It is a further object of the invention to provide a system foradditivcly or subtractively inserting the content of two mixed-baseregisters into a third mixed-base register.

It is still another object of the invention to provide a system fordecimal counting by means of mixed-base technique.

It is a further object of the invention to provide systems formultiplication of mixed-base members by successive additions, and, inthe alternative, by employing algorithms of congruence algebra.

Another object of the present inventionresides in the provision of asystem for congruence addition or multiplication in a single binarycounter, wherein units, tens, hundreds, etc., are added or multiplied interms of numbers congruent to the units, tens, hundreds, etc., in orderto reduce computing time.

It is another object of the present invention to provide methods ofmatrix addition, subtraction and multiplication of mixed'base numbers.

Still another object of the invention relates to systems for matrixconversion from mixed base numbers to single base numbers, such as, forexample, decimal numbers.

A further object of the invention resides in systems for conversion ofcomplex mixed-base numbers to numbers taken to conventional bases, suchas decimal or binary.

Still another object of the invention resides in the provision of asystem for converting decimal to mixed base notation, in a digitalcomputer.

It is still another object of the present invention to provide a systemfor converting from weighted digit system to a mixed-base system, bycounting down the contents of a register in one number system in termsof simply constructed words, and counting up in another register theequivalents of those words in the other number system.

The above and still further features, objects and advantages of thepresent invention will become apparent upon consideration of thefollowing detailed disclosure of specific embodiments thereof,especially when taken in conjunction with the accompanying drawings,wherein:

FIGURE 1 illustrates schematically'asystem for adding single pulses to amixed-base register, modulo 3, 4;

FIGURE 2 illustrates schematically a decimal counter employing twomixed-base rings; I

FIGURE 3 illustrates in block diagram a multiple decade registeremploying mixed-base decade counters; FIGURE 4 illustrates in blockdiagram a system for subtracting in mixed-base notation;

FIGURE 5 illustrates in block diagram a system alternative to that ofFIGURE 4 for subtracting a mixed-base notation;

FIGURE 6 illustrates in block diagram a system for multiplying inmixed-base notation; I

FIGURE 7 illustrates in block diagram a system for inserting largenumbers into a ring counter in terms of modulo 9, 10, 11.

FIGURE 10 is a block diagram of a system for congruence multiplicationof mixed-base numbers;

FIGURE 11 is a block diagram of an additive matrix, employing mixed-basenotation;

FIGURE 12 is a block diagram of a multiplicative matrix, employingmixed-base notation.

FIGURE 13 is a block diagram of a system of multiplication employingmatrix techniques, for numbers expressed in mixed-base notation;

FIGURE 14 is a block diagram of a mixed-base to decimal conversionsystememploying matrix techniques;

FIGURE 15 is a block diagram of a system for converting mixed-base wordsto decimal words by'a process 'of counting down in terms of significantmixed-base Words. I g g 0 FIGURE 16 is a block diagram of a modificationof the system of FIGURE 15, arranged for a tri-modulo system.

FIGURE 17 is a block diagram of modification of the system of FIGURE 16.

FIGURES l8 and 19 are tables showing the equivalences of certainnumbers, mixed modulo base 5, 6, 7

. to decimal notation and vice versa, which are significant toconversion of the notations.

FIGURE 20 is a block diagram of a system for mixedbase to decimalconversion arranged to employ all the significant numbers of FIGURE 18in converting from mixed-base to decimal notation; I

' FIGURE 21 is a block digaram of a system for decimal to mixed-baseconversion, employing the principles of FIGURE 20; and

FIGURE 22 is a block diagram of a system of mixedbase to binaryconversion, employing the principles of FIGURE 20. i Referring now morespecifically to the accompanying drawings, in FIGUREI is illustratedschematically a system for converting a count to a mixed-base word, theinitial count being in decimal notation, and the mixed base wordemploying the bases 3 and 4, or in mathematical terminology, a basecongruent mod 3, 4. A series circuit is provided, comprising seriatim, avoltage source 1, a switch 2, a condenser 3 and a resistance 4. Thejunction of the voltagesource 1 and the resistance 4 is grounded and anoutput lead 5 derived from the junction of condenser 3 and resistance4., Accordingly, closure of the switch 2 will result in charging currentflowing through the condenser 3. If circuit values are properlyselected, charging will be step wise and short pulses of current willflow in resistance 4, corresponding with voltage pulses applied to lead5. Obviously, other devices may be provided for generating a short pulsecurrent for each closure of a switch, and the specific circuitillustrated and described is intended to be exemplary only, andcorresponds to one possible embodiment of a pulse source.

The pulses P applied to lead are applied simultaneously and in parallelto two ring counters 6 and 7, of which counter 6 is mod 3 and counter '7is mod 4, i.e., ring counters 6 and 7 will repeat after attaining countsof 2 and 3, respectively, starting from zero count. A table showing thesettings of counters 6 and 7 for various numbers of input pulses, is asfollows:

By observing the states of counters 6 and 7 following the count, and byreference of the table provided, the combined counter readings may beinterpreted decimally, or in terms of number of counts in decimalnotation.

Switch 8 serves to reset the ring counter 6, 7, to 00 states, in amanner per se well known, and for that reason not especially describedor illustrated.

While the system of FIGURE 1 has a total capacity without redundance of12 i.e., of the product of the moduli employed, it is sometimesdesirable to employ mixedbase techniques in a decimal ring counter,i.e., to provide a decimal counter employing rings mod 3 and 4, a carryand reset pulse being provided when the count is attained. Otherwisestated, it is sometimes desirable to provide a count of 10 ring counter,the internal arrangement of which is such that the counter employsmixed-base techniques, in which case the most appropriate moduli toemploy would be 3 and 4.

In the system of FIGURE 2, two rings mod 3 and 4 are provided which areidentified by the reference numerals 6 and 7 and are arranged to countpulses in parallel, applied via the lead 9. Reference to the above tablefor a 3 by 4 mixed-base system indicates that ten in decimal notation is1, 2 in the 3 X4 mixed-base system.

Accordingly, the units output lead of ring 6 and the two output lead ofring 7 are applied to an AND gate 10 leading to an output lead 11, onwhich is provided the desired output carry pulses. The output pulses arealso applied to a permute to 0 amplifier 12, which after a suitabledelay required to complete the output carry pulses on lead 11, appliesreset pulses to counter 6, 7, resetting these to 0 ready for applicationof further input pulses applied to lead 9. The carry pulses may beapplied to further decades to yield any required counting capacity, bycascading.

The system of FIGURE 2 in essence constitutes or is functionally adecimal ring counter, employing mixedbase notation. Such counters may becascaded, employing the system in which all pulse counters are appliedto lead 9, and in which carry exists from one counter to the next ofhigher decimal order. While such counters have many applications, theyrequire a counting pulse for each event to be registered, andaccordingly, where a very large number of events is required to becounted, the read-in time becomes appreciable. Read-in time may begreatly reduced by employing parallel input techniques employingmixed-base decade counters.

Referring now more particularly to FIGURE 3 of the accompanyingdrawings, there is illustrated a series of four decade counters, theunits counter of which is identified by the reference numeral 33, thetens counter by the reference numeral 34, the hundreds counter by thereference numeral 35, and the thousands counter by the reference numeral36. Each of the counters 33, 34, 35, 36 is a counter of the typeillustrated in FIGURE 2 of the accompanying drawings, i.e., a decimalcounter employing mixed-base techniques, and moduli 3 and 4. The unitspulses accordingly are applied over a lead 37 to the counter 33, and asindicated by the double arrows 33 are applied simultaneously to the tworings of the counter. Tens pulses are similarly applied by a lead 39 tothe tens decade counter 34, hundreds pulses are applied by a lead 4th tothe hundreds decade counter 35 and thousands pulses are applied by alead 41' to the thousands decade counter 36. It follows that only onepulse is required to insert a count of 1000 into the cascaded units, onepulse is required to insert a count of into the system, one pulse isrequired to insert a count of 10 into the system and a single pulseinserts single units into the system, in accordance with that one of theleads 37', 3%, 40, 41 to which the pulses are applied. A carry pulselead 42 inserts overage or carry pulses from the counter 33 to thecounter 34, a corresponding carry lead 43 applies overage or carrypulses from the counter 34 to the counter 35 and in a similar manner acarry lead 44 applies overage or carry pulses from the counter 35 to thecounter 36.

Clearly, if in the counter of FIGURE 2. the AND circuit 10 wereconnected at its two input leads for states 2 and 0 of the rings ti and7 respectively, the counter of FIGURE 3 would be a cyclic counter ofbase i5 and would then operate with respect to a common base 8 numericalread in. Hence, the system may be applied to any desired base and is notlimited to decimal no tation.

The problem exists in computers of reading a number into a firstcounter, reading a second number into a second counter and thereaftersubtracting the count read in the first counter from the count read intothe second counter, or otherwise stated, of reducing the count of thesecond counter by the count of the first counter.

A system for performing this operation, employing mixed-base techniques,is illustrated in FIGURE 4 of the accompanying drawings.

In the system of FIGURE 4 there is employed a first counter,constituting a subtrahend counter, 56, and employing a modulo 3 ring,51, and a modulo 4 ring, 52. A minuend counter, 53, similarly employs amodulo 3 ring, 54, and a modulo 4 ring, 55. The moduli 3 and 4 have beenselected merely as illustrative, and two rings per counter have beenselected for illustration, in order to simplify the exposition. It willbe apparent that the principles of the system of FIGURE 4 may beextended to other moduli, and to numbers of moduli other than two.

The lead 56 constitutes a subtrahend read in lead, to which is appliedpulses, the number of pulses being of the desired subtrahend. Thesepulses are applied by switch 57 in its lower position to the counter 50,i.e., to the rings 51 and 52. in parallel. The lead 58 constitutes aminuend read in lead through which pulses to be counted are applied by aswitch arm 59, in its lower position, to the counter 53 i.e., to rings54 and 55 in parallel. When read in has been completed, or at any timethereafter, the switch 61} is closed applying bias voltage from thesource 61 to gate 62. and opening the latter. Simultaneously withclosure of switch 60, or previously thereto, the switch arms 57 and 59'are thrown to their upper positions. When gate 62. is closed pulses froma clock pulse generator 63 are applied via the gate 62 to the counters50 and 53 in parallel. The zero position of ring 51 and the zeroposition of ring 52 are jointly applied to an AND gate 64, the output ofwhich appears on a lead 65 and is applied to the gate 62 as a stopsignal. Zero position of thering 54 and zero position of the ring 55 arejointly applied to a NOT AND gate 66, which issues into a negativenumber alarm 67 in the form of a suitable indicator, which whenactuated, indicates that recomplementation is to take place.

Once two numbers have been inserted intbe registers 50 and 53, and thepulses provided by the clock pulse generator 63 fed to the registers 50and 53, it will be clear that the register 50 will continue to step inresponse to the clock pulses in an additive direction until its positionis reached, at which time the gate 62 will be closed and the stepping ofregister 50 will terminate. The register 53 will be steppedsimultaneously with the register 50, and its stepping action willterminate when the gate 62 is closed. Accordingly, the register 50comprising counters 51, 52 will terminate action with the count of 00,but the register 53 will in general have some different count than 00 atthe termination of the clock pulsing operation. i

We may assume, for purpose of explanation only, that the decimal number6 is the minuend inserted in' the register 53 and the subtrahend 2 isinserted into register 5i). On the basis of this assumption, the stateof rings 51, 52 is 2-2, while the rings 54, 55 after read-in will read02. Application of clock pulses to the several counters new steps theseveral counters progressively through their cycles. The register 50 iscausedto step back to 00 position. Since the latter started at 2-2 thestates through which it will pass are as follows: 0-3, 1-0, 2l, O-2, 13,2-0, O- l, 1-2, 2-3 to state 00. At this point, the AND circuit 64 stopsthe clock pulses. The number of clock pulses which were required wasthus ten in number. These clock pulses simultaneously stepped rings 54and 55 from their initial registration of (L2 thru successive states toan eventual reading of l-().

The reading 1-0 at register 53 corresponds in mixedbase notation with adecimal value of 4, which is in fact the required difference. The NOTAND circuit 66 is utilized to detect the passing of mixed-base Word ()0in rings 54 and 55, to inform whether the value observed or registeredonrings 54 and 55 are in fact, true values, or are complements of the truevalue. If, for example, the mixed base number ()0 is not passed duringthe subtractive process, the negative number alarm number circuit 67 isenergized. This circuit-may take the form of a neon bulb, in a simpleapplication ofthe invention, and indicates that the registered resultmust be recomplemented. For example, if'an attempt were made to subtractfour from three, the eight clock pulses which will result would leave adifference of rings 54 and 55 of 23 in mixed-based form. Thiscorresponds to the decimal number 11, which should be recomplemented to-1, complementing in the mixed-base form involving merely the noting ofthe difference between the number to be complemented and thesystem'capacity, which in the instant example is 12.

The system of FIGURE 4 may also be employed to performthe algorithm ofaddition. In order to add, it is merely necessary to feed the aug'endinto the minuend register 53 and the addend into the subtrahend register50, the latter, however, in complementary form.

It is well known that ring counters areayailable, which are able tocount in the forward direction upon receipt of positive pulses and inthe reverse direction upon receipt of negative pulses. It is essential,in the system of FIGURE 4, that for performing the addition process,either the addend or the augend must be complemented, or reverse codedat some step in the procedure. This may be accomplished by reading ineither the addend 10 or augend in complementary fashion, in which casethe system of FIGURE 4 will directly yield a sum in the register 53. Analternative technique would be to feed stepping pulses deriving from thegate 62 in inverse polarity to one or the other of the registers, butnot to both, in which case the necessary complementary function wouldautomatically result. The techniques which may be employed for a givenpractical machine may be selected at will by the designer thereof.Having selected a given technique, the negative number alarm 67 willinform the operator when a registered quantity in register 53 must berecomplemented. For example, if a decimal number 5 is to be added to thedecimal number 3, reverse stepping of the register 50 after the read-inhas been accomplished will allow 5 clock pulses to appear through gate62, assuming that the subtrahend register 50 started from read-in of2-0, which is equivalent to the decimal sum 8. In a case of addition asdescribed, the NOT AND circuit 66 must be interpreted in oppositefashions of that previously explained i.e., the passing of 00 locationin register 53 implies the necessity for recomplementing the sum, and isthe opposite for subtraction. Obviously, the alternative expedientimplies employing an AND gate in place of the NOT AND gate 66, givingthe indication of the negative number alarm 67, likewise, acorresponding significance.

Where two numbers which are to'be added or subtracted one from the othermay be made available in se quence, a simpler system than thatillustrated in FIGURE 4 of the accompanying drawings may be resorted to.In the system of FIGURE 5 of the accompanying drawings there isindicated a ring 6 modulo 3 and a ring 7 modulo 4, the inputs to whichare applied in parallel. A pulse input terminal is indicated at70.Intermediate the input terminal 70 and the rings 6 and? is connected apulse polarity inverter 71, which issues to a switch terminal 72. Aparallel circuit or lead 73 connects the terminal 70 dircctly with aswitch contact 74. Switch contacts 72 and 74 may be selected by means ofa switch arm 75, whichis in turn connected with the input leads to therings 6 and 7. When his desired to add twoseries of pulses, which areavailable in sequence, switch arm 75 is placed in'its lower or addposition and the two series of pulses applied to the inputterminal 7 0.Thefirst series of pulses step the rings 6 and 7 to positionscorresponding with the number of pulses of the first series, and thesecond series arriv ing after the first series continues the steppingaction of the rings 6 and 7. The final position of the lattercorresponding with the sum of the pulses. On the other hand, if it isdesired to subtract the second series of pulses from the first series ofpulses, the switch 75 is placed in its upper or subtract position, andthe input pulses are applied via the inverter 71 to the rings 6 and 7.The rings 6 and 7 are assumed to be made up of circuit elements of suchnature that positive impulses causes each ring to step in one direction,while negative pulses causes each ring to step in the oppositedirection. In the latter case the first series of pulses inserts anumber into the rings 6,7 in mixed-base notation, while the secondseries of pulses reduces that number by the subtrahend required.

The AND circuit 76 has its input terminals connected to the 00 positionsof the rings 6 and 7, and includes an output lead 77,to which anindicator or other device may be connected. In the case of subtraction,the AND indicator may be employed to indicate the need forrecomplement'ation, while in the case of. successive additions the ANDcircuit may be employed to indicate that overflow of the mixed-basecapacity of the system has taken place. e I I Were it desired to comparetwo numbers to determine which is the larger, the first number may beinserted in a additive sense in terms of the number of pulsescorresponding with the number, and the second number may be inserted ina subtractive sense in terms of the number of 1 1 pulses correspondingwith the number. In such cases, if the lead 77 is supplied with a signalby the AND gate '76, it will be an indication that the second number wasthe larger. n failure of such an indication, the first number may beknown to be the larger.

The systems or arrangements of FIGURES 1 to 5, inclusive, relateentirely to addition and subtraction. One of the important functions ofa computer is to multiply two numbers which may have been previouslyinserted in registers. The process of multiplication is essentially aprocess of repeated addition. For example, the number 3 may bemultiplied by the number 2 by adding the number 3 to the number 3.FIGURE 6 of the accompanying drawings is a block diagram of a system forperforming multiplication, employing mixed-base techniques and computingelements, multiplication being performed in terms of repeated additions.

In FIGURE 6, the lead 80 is a multiplier read-in lead, while lead 81 isa multiplicand read-in lead. With switches 82 and 83 in their upperpositions, a multiplier may be read in to the mixed-base multiplierregister 84 and a multiplicand may similarly be read in to the mixedbase register 85. The fuction of the system is then to multiply thereading of register 84 by the reading of register 85, accumulating theproduct in a mixed-base product accumulator register 86, on the commandmultiply. This command is given when the switch 87, which is normallyopen, is closed, and the switches 83, 32 are simultaneously placed intheir lower positions. Preferably the switches 33, 82, and 87 may beganged, as by suitable linkage 88. Placing the switch 82. in its lowerposition connects the input of the mixed-base multiplier register 84 tothe output of a step down inverter 89, which serves to convert thepolarity of pulses applied to the input thereof prior to application tothe register 84, so that pulses applied from the ep down inverter 89 tothe register 84 will serve to reduce the total amount registeredtherein. To this end, the register 34 is of the reversible type, whichadds in response to pulses of positive polarity and which subtracts inresponse to pulses of negative polarity. Opening of the switch 83 merelyserves to disconnect the register 85 from the multiplicand readin lead81. Closure of the switch 87 connects the register S to the output of agate 96. The gate 9!) in turn supplies pulses to the register 85 from aprimary clocr pulse generator 91, while the switch 87 is closed,provided the gate 90 is then open.

The register 85 is the type which is capable of being readout withoutdestroying its contents. Techniques for obtaining nondestructive readoutof registers are well known to those skilled in the computer art, andtypically involve a localized process of regeneration. Readout pulsesare applied to the register 85 from the primary clock pulse generator 91via the normally open gate 98 in such sense as to cause the reading ofthe register 85 to return to O, readings of the register 85 beingsimultaneously transferred to the register 86 in additive fashion.

As soon as the readout of the contents of the multiplicand register 85has been accomplished, a suita le AND GATE in the register, connected tothe 00 positions of the register 85, applies a step pulse to lead 92.The step pulse applied to the lead 92 traverses the reset circuit 93which causes the register 85 to resume its original reading.Simultaneously the ()6 step pulse applied to lead 92 is fed through thestep down inverter 89 and through switch 82, now in its lower position,to the mixed base multiplier register 84, reducing the contents of theregister 3 by a single step for each complete readout from themultiplicand register 85 to the accumulator register 86.

The readout process continues, repetitively, the original values setinto the register 85 being read out into the register 86, the register85 being then reset to its original reading, and its reading being againreadout to register 86.

Concurrently, the reading of the rnixed-base multiplier register 84 isbeing reduced by one unit for each complete readout. The process ofmultiplication by successive additions, as hereinabove described,continues until the mixed-base multiplier register 84 is emptied, atwhich time it generates a ()0 stop pulse, at lead fill, this stop pulseclosing the gate 9t: and accordingly terminat ing the multiplicativeprocess. The 00 stop pulse applied to the lead $3 is also applied to theclear circuit 94, which generates clearing pulses for application vialead to the mixed-base nondestructive multiplicand register 85, clearingthe latter completely, and conditioning same for a further operation orfor insertion of further data therein.

A problem of primary importance to the construction of computers basedon mixed base techniques is that of conversion to mixed base notationfrom other notations. A most important problem in this respect is theproblem of converting from decimal notation to mixed-base notationrapidly, in order to reduce computing time. It will be clear when thetotal capacity of a mixed-base register is relatively small, that nodii'liculty is encountered in feeding into the register a number ofpulses corresponding with the decimal number to be converted. Each ringof the register is then subjected to all the pulses in the number.However, where extremely large numbers must be handled, this techniqueis not practical. Attention is directed to a single ring of a mixed-baseregister. This ring must be subjected to a sutiieient number of pulsesto attain a final position which is congruent to the desired decimalnumber modulo the modulus of the ring. For example, consider a ringwhich has nine positions i.e., a ring modulo 9. Regardless of how manypulses are applied to the ring, the final position of the ring must beone of the nine possible positions. It appears to be totally incongruousto apply a tremendously large number of pulses to a ring counter inorder to obtain ultimately a position of the counter which must be oneof a very small number of values. A simple device for reducing the totalamount of read-in time to a ring is illustrated in FIGURE 7 of theaccompanying drawings. For purpose of example only, it is assumed thatthe decimal number 124 is to be read into 'a modulo 7 ring. The readoutis arranged so that instead of expressing the decimal number 124 as asequence of 124 clock pulses applied to the modulo 7 ring, the hundreds,tens, and units of the decimal number applied by a separate circuit tothe ring, i .e., the ring is fed by decimal columns. It can be shownmathematically that :2 mod 7, i.e., that one hundred divided by 7 leavesa remainder of 2. Similarly, 1053 mod 7. It then, for each hundreds unitin a given decimal number, two pulses to be transmitted to a ring of 7,and three pulses for each tens unit, while a single pulse is applied foreach unit present in the decimal number, the ring 7 will assumeprecisely the same position as it would have done had a sequence orseries of pulses equal to the decimal number desired to be inserted beenapplied are by one to the ring of 7. The above recited consequences ofcongruence algebra are implemented in the system of FIGURE 7.

Referring now more particularly to FIGURE 7 of the accompanyingdrawings, a ring of 7, identified by the ref erence numeral 1%, isprovided, in which is to be inserted a decimal value containinghundreds, tens, and units. A single pulse, as 101, is applied to aterminal lilf. for each hundredths unit. Similarly a single pulse isapplied to terminal 1&3 for each tens unit and "a single pulse toterminal 104 for each unit in the decimal numher. The terminal 102 isconnected with an input lead 165 for the ring of 7, Mid, by a doublepulse generator 1%, i.e., a generator which transmits two pulses foreach input pulse applied thereto. The terminal 103 is connected to thelead via a triple pulse generator ltfl i.e,, a pulse generator whichtransmits three pulses for each input pulse applied thereto. Theterminal 104 is directly connected to the lead ltlS.

13 Returning to our original example, i.e., the insertion of the number124 into amodulo 7 register, a single pulse is applied to the terminal102, two pulses to the terminal 103 and four pulses to the terminal 104.The single pulse supplied to the terminal 102 is translated to twopulses by generator 106' and two pulses are accordingly supplied to thelead 105 and thence to the ring of 7, 100. p The two pulses supplied tothe terminal103 are translated into six pulses by the generator 107 andthese six pulses are supplied to the ring of 7, 100. The four pulsessupplied to the terminal 104 are directly supplied to the ring of 7.Accordingly, the total number of pulses supplied to the ring 100 is 12.1225 mod 7, and accordingly the ring of 7 will show a count of which isin turn directly congruent to the decimal number 124 modulo 7.

It will be noted that a total of 12 pulses suliiced to read into thering of 7 the decimal number 124. Since corresponding techniques may beapplied to rings of any desired modulo, by utilizing appropriatepulse'generators or pulse multipliers, it will be evident that aregister cont ainingany number of rings may be fed in an extremely shorttime by a relatively short sequence of pulses representative of anextremely large number, and in efiect, the total extent of the number tobe inserted bears very little relation to the total number of pulsesrequired to insert the number into the several rings.

The technique illustrated in the system of FIGURE 7 of the accompanyingdrawings leads to certain conclusions with respect to the designofmixed-base computers. For example, if a modulo 11 ring is employed in aregister, the hundreds column of a decimal number, since it is congruentto 1 modulo 11, can be fed directly to the ring of 11, i.e., 10051 mod11. The tens column isactually congruent to minus 1 modulo 11 (1021 mod11) and thus can be fed directly to'the ring 11 through an inverter. Theunits column of a decimal number obviously must be fed directly to thering of 11. In fact, the hundreds column advances the ring of 11 oneplace for each hundredths unit, while the tens column subtracts one fromthe ring of 11 or steps the ring of 11 backward for each tens unit. In adecimal to mixed-base conversion system, a ring modulo 11 is anextremely valuable and convenient ring to utilize. Similar consequencesmay be obtained utilizing a ring of ten and a ring of nine, i.e., solong as the moduli of the system are very close to the base of thesystem from which the conversion is to be efiiected, the complexity ofthe system is maintained at an extremely low level. To provide furtherexamples, the decimal number 134 may be inserted in a ring of 11 byinserting 5 forward stepping pulses and 3 reverse stepping pulses.Decimal number 30 would be registered in a ring of 11 by providing threebackwardstepping pulses. Obviously, since a ring of ten is congruentmodulo 0 to hundreds and tens, in the later case only the units need beentered in the registerj Reference is made to FIGURE 8 of theaccompanying drawings for a system for inserting decimal numbers into aring of 11.3 The ring of 11 itself is identified by the referencenumeral 110. Terminals 111, 112 and 113 areemployed for feeding pulsescorresponding with the hundreds, tens, and units, of a decimal numberrespectively to the ring of 11, 110. The hundreds pulses are applieddirectly from the terminal 111 to the ring of 11, 110, and the units aresupplied directly'from the terminal 113 to the ring of 11, 110. The tenspulses are supplied -from the terminal 112 via an inverter 114 to thering ofll, 110.

It will be appreciated that both in the system of FIG- URE 7 and in thesystem of FIGURE 8, it is essential that the various pulses suppliedinparallel to the rings not overlap in time. This may be readilyaccomplished by proper design of readout devices, or where the read- 1twill also be appreciated that decimal columns of significance 1000-;10,000; 100,000; etc., can be handled Hundreds, tens and units pulsesare applied, respec-' tively, to terminals 111, 112, 113, sequentially,or otherwise in non-interfering or non-overlapping relation. The unitpulses are applied to ring of 11, 110, to ring of 10, 115, and to ringof 9, 116, since addition of unit to a mixed-base register requiredaddition of unity to each counter or ring thereof. Application to ring116 is via OR gate 117.

Since 1050 mod 10, and 10050 mod 10,110 pulses need be inserted into thering of ten 115, for counts of n Since 1OE-1 mod 1l, and E+1 mod 11, itis required to subtract one pulse from ring for each count of 10, add apulse to ring 116 for each count of 100 and add a pulse to each of rings110 and 116 for each count of 100. Accordingly, terminals 111 and 113are connected via an OR gate 118 to ring of 11, 110. Since 1051 mod 9,and 10021 mod 9, terminals 111 and 112 are connected to OR gate 117, andthence to ring of 9, 116.

, In the system of FIGURE 10 is illustrated one type of multiplicationof twon-umbers set into rings of a mixedbase system. For clarity ofpresentation, and to avoid duplication, the system is shown as appliedto a bi-modulo system,the extension .to a tri-modulo system being thenobvious, and requiring merely duplicationof the equipment employed forbi -modulo multiplication.

A clock provides step-down pulses to a first ring of seven 126. For eachclock pulse the ring of seven 126 steps back one place, until a zeroreading is attained when a closure pulse is applied to a bi-stable gate127 via lead Pulses are passed bygate 127, while open, to areadoutdevice 129, which reads out the setting of ring 130 which is aringcounter modulo 7, into an accumulator ring of 7, 131, by non-destructivereadout.

Successive read-outs occur from ring 130 into ring 131, for a number oftimes adequate to step ring 126 back to zero, when closure of gate 127stops the process of accumulation.

Similarly, step down pulses are applied from clock pulse generator 125to a ring of 8, 132, which, on attaining count of zero, closes anormally open gate 133. Each clock pulse, while gate 133 is open,efiects a non-destructive read-out of ring of 8, 134, by energizingread-out device 135, which transfers the read-out to accumulator ringofseven, 131 and ring of eight, 136.

There is thus inserted into ring of seven, 131, and ring of 8, 136,respectively the product of the readings of rings of 7, 126, and 130,and rings of 8, 132, 134, respectively,

in all cases to the proper modulus. It can then be shown,

by congruence algebra, that the readings of rings 131 and136, representproducts in mixed base notation, of the readings of rings 132x134 and126x130, respectively. The congruence algorithm involved is, that if aabmod m, and cad mod m, then aczbd mod m.

MATRIX ADDITION The algorithm involving congruences, and hence mixedbasecomputation, permit the increase of computer speed by means of matrices.For purpose of example only, matrix addition of two rings, modulo 3, isillustrated and described, i.e., it is assumed that a residue modulo 3has been inserted in one ring of 3, and another residue modulo 3 hasbeeninserted in another ring of 3, and that the contents of the ringsare to be added.

